UC Berkeley
Power Electronics Group

Power Electronics at UC Berkeley

The Power Electronics Group is in the Electrical Engineering and Computer Science (EECS) department at the University of California at Berkeley. Professor Seth Sanders advises the group on research in the areas of power electronics, switching converters, and energy systems.

Group Contact Info:

Power Electronics Group
550 Cory Hall
Berkeley, CA 94720-1772

Professor Seth Sanders

Seth R. Sanders received the S.B. degrees in electrical engineering and physics and the S.M. and Ph.D. degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1981, 1985, and 1989, respectively.

He was a Design Engineer at the Honeywell Test Instruments Division, Denver, CO. Since 1989, he has been on the faculty of the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, where he is presently Professor. His research interests are in high frequency power conversion circuits and components, in design and control of electric machine systems, and in nonlinear circuit and system theory as related to the power electronics field. He is presently actively supervising research projects in the areas of flywheel energy storage, novel electric machine design, renewable energy, and digital pulse-width modulation strategies and associated IC designs for power conversion applications. During the 1992 to 1993 academic year, he was on industrial leave with National Semiconductor, Santa Clara, CA.

Dr. Sanders received the NSF Young Investigator Award in 1993 and Best Paper Awards from the IEEE Power Electronics Society and the IEEE Industry Applications Society. He has served as Chair of the IEEE Technical Committee on Computers in Power Electronics, and as a Member-At-Large of the IEEE PELS Adcom.
Professor Seth Sanders

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2014 Group Photo
Group in April '14: (left to right) Jason Poon, Daniel Gerber, Prof. Seth Sanders, Achintya Madduri, Yongjun Li, Mervin John
2012 Group Photo
Group in April '12: (left to right) Kun Wang, Nic Beutler, Daniel Gerber, Prof. Seth Sanders, Mike He, Denise Loeder, Achintya Madduri, Mervin John, Hanh Phuc Le, Alan Harbottle (UG)
2007 Group Photo
Group in May '07: (left to right) Jason Stauth, Tim Loo, Artin Der Minassians, Kun Wang, Michael Seeman, Thura Lin Naing (UG), Evan Reutzel, Vincent Ng, Charles Wu (UG), Dr. Seth Sanders. Not Shown: Mike He

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Research Areas

Previous Research Areas

Pulse-Density Modulation for RF Transmitter Applications

Jason Thaine Stauth and Seth R. Sanders
Conventional wireless transmitters use linear (class-A, AB) power amplifiers to perform amplitude modulation for high-datarate standards such as 802.11a/g/n that require high spectral efficiency. In these applications, the power amplifier (PA) typically operates with average efficiency in the range of 5% due to strict linearity requirements [1-4]. This work is focused on new transmitter architectures that use pulse-density modulation to perform linear amplitude modulation of the RF carrier with a nonlinear power amplifier (PA). Advantages of this approach include high linearity for wideband standards, high efficiency across the range of output power, and a simplified pure-digital implementation resulting in small die area. Our approach uses deterministic (programmed) pulse density modulation operating at the RF carrier frequency, combined with baseband ? modulation operating at baseband frequencies. The multi-stage approach shapes quantization noise away from the signal band allowing effective reconstruction of high peak-average power ratio (PAPR) waveforms with minimal digital processing power. The switching PA achieves output power levels comparable to WLAN or Bluetooth with average efficiency approaching 20% for the entire transmitter including power consumption for the PA, PA driver, and digital processing circuitry.

More information: http://www.eecs.berkeley.edu/~jtstauth
Figure 1: Die photo of pulse-density modulated transmitter
  • [1] A. Jerng and C. G. Sodini, "A Wideband Delta-Sigma Digital-RF Modulator for High Data Rate Transmitters," IEEE Journal of Solid State Circuits, Vol. 42, August 2007, pp. 1710-1722.
  • [2] F. Wang, D. Kimball, D. Y. Lie, P. Asbeck, and L. E. Larson, "A Monolithic High-Efficiency 2.4 GHz 20 dBm SiGe BiCMOS Envelope-Tracking OFDM Power Amplifier," IEEE Journal of Solid State Circuits, Vol. 42, June 2007, pp. 1271-1281.
  • [3] J. T. Stauth and S. R. Sanders, "Optimum Biasing for Parallel Hybrid Switching-Linear Regulators," IEEE Transactions on Power Electronics, Vol. 22, September 2007, pp. 1978-1985.
  • [4] J. T. Stauth and S. R. Sanders, "Power Supply Rejection for Radio Frequency Amplifiers: Theory and Measurements," IEEE Transactions on Microwave Theory and Techniques, Vol. 55, October 2007.

Ultra-Low-Power Switched-Capacitor DC-DC Converters

Michael Douglas Seeman and Seth R. Sanders
Switched-capacitor power converters have been used in IC designs for years, but the fundamentals of the converters' operation have not been well defined. This research formally specifies the structure of switched-capacitor converters and develops a method for easily determining the performance of these converters. These performance metrics can be used to optimize component values in converters as well as to compare different converter topologies. The analytical tools developed will aid construction of several switched-capacitor circuits [1].

The first IC we built using a switched-capacitor converter is an integrated switched-capacitor DC-DC converter for use with the PicoCube project. The PicoCube system uses an average of 6 microwatts at very low duty cycles (high relative peak power) at three voltage rails. This converter will rectify an energy scavenger source and supply the three voltage rails from a single small rechargeable battery. An integrated circuit implementing this converter has been designed, manufactured, and tested. Peak efficiencies of 80% have been obtained through empirical results [2].

In the future, multi-level switched-capacitor circuits will be considered. Instead of being limited to a single conversion ratio, these enhanced topologies can efficiently be configured to produce a wide range of conversion ratios. The applications of such a converter are widespread. They have been typically used as inverters to drive motors or to create other ac waveforms. However, they can also be used to add efficient regulation to typical DC-DC applications. An IC using a multilevel switched-capacitor converter will be fabricated in future work.
  • [1] M. D. Seeman and S. R. Sanders, "Analysis and Optimization of Switched-Capacitor DC-DC Converters," IEEE COMPEL, July 2006.
  • [2] M. D. Seeman, S. R. Sanders, and J. M. Rabaey, "An Ultra-Low-Power Power Management IC for Wireless Sensor Nodes," IEEE CICC, September 2007.

12 V-to-1.5 V Switched Capacitor dc-dc Converter in a Submicron CMOS Technology

Vincent Wai-Shan Ng, Seth R. Sanders and Michael Douglas Seeman
This research explores the design and development of CMOS-based switched capacitor (SC) dc-dc conversion circuitry aimed at applications traditionally addressed with the ubiquitous buck converter. The traditional buck converter requires at least one substantial inductor and transistors with voltage rating matched to the input source voltage, which may be costly to integrate in a submicron CMOS technology. The traditional buck converter also suffers from low efficiency or poor power device utilization when used in a high-conversion-ratio application. Further, buck converter efficiency degrades rapidly in low-power modes unless additional special modes (like PFM) are enabled. SC dc-dc converters, on the other hand, can sustain high efficiency with a high conversion ratio, and also over a very wide load range. Moreover, SC dc-dc converters do not require any magnetic or high voltage transistors; each power transistor needs to only block a fraction of the input voltage, thus allowing a high voltage dc-dc converter to be built in a submicron technology with native transistors. To prove our concept, we built a 12 V-to-1.5 V SC dc-dc converter in a 0.18 m CMOS technology with a peak output current of 1.5 A and a peak efficiency of 98%. This converter is ideal for the point-of-load application in which a dc-dc converter is placed close to an associated load.
Figure 1: Efficiency versus output load condition

Low Cost Solar Thermal Electric Generation

Mike M. He, Seth R. Sanders, and Artin Der Minassians
Two major barriers impede the widespread adoption of renewable energy technology on a large scale. The first is high cost relative to traditional energy sources under current market conditions. The second is that renewable sources have intermittent and fluctuating power output. A system that offers a solution to these problems has the potential to achieve significant adoption.

One technology that has the potential to overcome these challenges is a solar thermal electric generation system with a Stirling engine and integrated energy storage. The goal of the system is to achieve a capacity cost of $1/W, generally considered a major milestone that makes solar energy cost-competitive, by employing low-cost materials, simple manufacturing, and careful design. Inherent thermal energy storage provides a means of generating continuous, stable power output. By addressing the barriers stated previously, the system has the potential to become a significant source of renewable energy.

Two low-power prototypes have been built, one a single-phase engine and the other a three-phase engine. Current work is focused on desiging a high power prototype.

Single Phase Stirling Engine
Figure 1: Single Phase Stirling Engine Prototype
Three Phase Stirling Engine
Figure 2: Three Phase Stirling Engine Prototype

Integrated DC-DC Conversion

Hanh-Phuc Le, Prof. Seth Sanders, Prof. Elad Alon
CMOS chips have evolved to operate at steadily lower supply voltages and increasing power densities, leading to drastic reductions in the required impedance of the supply distribution network. For example, todays 1V, 100A microprocessors require a supply impedance of ~1mOhm, which is extremely challenging to achieve across a broad range of frequencies. Indeed, this impedance requirement limits the amount of current that can be efficiently delivered onto the die, limiting the ability to improve performance by integrating additional cores. Furthermore, supporting multiple independent supply voltages on the die (for improved power management) is currently very challenging due to the impedance degradation associated with heavily partitioned package power planes.

In order to overcome these challenges, in this project we will study, design, and fabricate fully integrated voltage converters that maximize the overall efficiency and robustness of high-performance digital chips. To allow for multiple on-chip supply voltages and simplify the board- and package-level power delivery networks, we will focus on an architecture consisting of many distributed, fully-integrated switching regulators (for efficient conversion of a single external high-voltage supply) combined with parallel linear regulators to control the AC impedance. Since the parallel linear regulator can be designed to spend minimal power in setting the effective supply impedance [1], the switching regulator can be optimized purely for conversion efficiency. As an additional benefit, integrating the voltage converter onto the die relaxes the impedance requirements of the global supply, potentially leading to significant simplifications in the complexity of the package and PCB power distribution networks.

Energy Efficient Wireless Transmitters: Polar and Direct-Digital Modulation Architectures

Jason T. Stauth and Seth R. Sanders
Conventional wireless transmitters use linear (class-A, AB) power amplifiers to meet linearity requirements for high-data rate, spectrally efficient standards such as 802.11a/g/n. In these applications, traditional power amplifiers (PAs) operate with average efficiency in the range of five percent, despite having the highest power consumption of any block in the radio architecture. This significantly impacts battery life and cost for portable systems, and adds to unnecessary power consumption in the wireless communications infrastructure.

This talk will focus on new transmitter architectures that use polar representation of the wireless signal to improve both performance and energy efficiency. The first part of the talk will discuss voltage regulation for power amplifiers, including the effects of power supply noise and the benefits of wideband regulation schemes. The second part will focus on pulse-density modulation (PDM) as a way to modulate the carrier amplitude with nonlinear power amplifier (PA) components. Advantages of this approach include high linearity for wideband standards, high efficiency across the range of output power, and a simplified pure-digital implementation resulting in small die area.

The talk will also describe the design and implementation of a highly-linear digital-polar system in 90nm CMOS. The amplitude is controlled with pulse-density modulation of the RF carrier. Phase information is provided with the RF clock. Two stages of noise shaping improve the performance of the digital transmitter. Second-order baseband sigma-delta modulation shapes in-band noise, reducing error-vector magnitude (EVM). Programmed pulse-density modulation, operating at 2.4GHz, forces much of the quantization noise power out of band, improving efficiency and spectral performance. The class-D PA achieves output power levels adequate for WLAN and Bluetooth, with peak efficiency of 38.5% at 2.4GHz, including power of the PA drivers and insertion loss of off-chip filter components. The system achieves rms EVM of 1.8-2.1% for pi/4DQPSK and 8DPSK test vectors while meeting the spectral mask and power requirements of Bluetooth 2.1+EDR.

ICs for Modern Power Management Applications

Angel Vladimirov Peterchev, Jason Thaine Stauth, Jianhui Zhang and Professor Seth R. Sanders
UC MICRO and National Science Foundation
Digital controllers for pulse-width modulation (PWM) converters are enjoying growing popularity due to their low power, immunity to analog component variations, ease of integration with other digital systems, ability to implement sophisticated control schemes, and potentially faster design process [1].

We are developing IC implementations of digital controllers for power converters that find applications in areas such as microprocessor voltage regulation modules (VRM) [2,3] and mobile device power supplies. We explore various topologies for the modules contained in a digital controller in order to provide a high-performance, low-cost solution. We have developed a very low power digital PWM (DPWM) generation module, PID control modules, and a novel low power ADC which is insensitive to switching noise and partially synthesizable. In the past year, we implemented a complete digital controller SOC for cell phone application with on-chip power switches (Figure 1) [4]. We are now investigating the implementaion of sophisticated estimation and control schemes using a combination of digital and analog processing, and special purpose analog-digital interface structures.
Figure 1: Block diagram of dual-mode buck converter IC
  • [1] A. M. Wu, J. Xiao, D. Markovic, and S. R. Sanders, "Digital PWM Control: Application in Voltage Regulation Modules," Proc. IEEE Power Electronics Specialists Conf., Charleston, SC, June 1999.
  • [2] A. V. Peterchev and S. R. Sanders, "Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters," IEEE Trans. Power Electronics, Vol. 18, No. 1, Pt. 2, January 2003, pp.301-8.
  • [3] A. V. Peterchev, J. Xiao, and S. R. Sanders, "Architecture and IC Implementation of a Digital VRM Controller," IEEE Trans. Power Electronics, Vol. 18, No. 1, Pt. 2, January 2003, pp.356-64.
  • [4] J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, "A 4 A Quiescent Current Dual-Mode Buck Converter IC for Cellular Phone Applications," accepted by ISSCC, San Francisco, CA, February 2004.

Voltage Regulation Modules for Modern Microprocessors

Angel Vladimirov Peterchev, Jason Thaine Stauth, Jianhui Zhang and Professor Seth R. Sanders
UC MICRO and National Science Foundation
The current trend in microprocessor design is characterized on the one hand by decreasing supply voltages (~1 V), regulation windows (~100 mV), and conversion ratios (1/12), and on the other hand by increasing supply currents (~100 A) and supply current slew rates (~300 A/us) [1]. These trends present a challenge to the design of microprocessor voltage regulation modules (VRMs). We are developing a control strategy that can meet these requirements, without using an excessively large number of output capacitors.

We have analyzed the response of the buck converter under fast output current transients, and we have developed sensing and control methods for its implementation with a digital PWM controller [2]. This analysis has been done in the framework of low effective series resistance (ESR) ceramic capacitors, which are the expected choice for the next generation VRMs. We have further explored the effect of power train parameter variations on the current matching among the phases of the converter [2].

We are currently working on discrete and IC implementations of a VRM controller with very fast response based on load current estimation and feed-forward. We are also considering IC implementations of advanced parameter estimation schemes.
  • [1] A. V. Peterchev and S. R. Sanders, "Low Conversion Ratio VRM Design," Proc. IEEE Power Electronics Specialists Conf., Cairns, Australia, June 2002.
  • [2] A. V. Peterchev, J. Xiao, and S. R. Sanders, "Architecture and IC Implementation of a Digital VRM Controller," IEEE Transactions on Power Electronics, Vol. 18, No. 1, Pt. 2, January 2003, pp.356-64.

Digital Control of PWM Converters

Angel Vladimirov Peterchev, Jason Thaine Stauth, Jianhui Zhang and Professor Seth R. Sanders
UC MICRO and National Science Foundation
Digital control has drawn increased attention to the area of pulse-width modulation (PWM) converters. Digital controllers (Figure 1) are attractive for their low power dissipation, immunity to analog component variations, compatibility with digital systems, and ability to implement sophisticated control schemes [1].

In this project, we have addressed system issues that are unique to digital control, such as the impact of the signal quantization in the feedback control loop. We have developed a set of conditions necessary for the elimination of limit cycles in digital controllers [2]. Further, we have analyzed and successfully used controlled digital dither to increase the effective resolution of digital PWM (DPWM) modules, while minimizing the dither ripple incurred on the regulated output voltage [2].

We have demonstrated implementations of the above-mentioned techniques with an FPGA-controlled voltage regulation module (VRM) for microprocessor applications [3], and a low power IC controller for cell phone applications [4].

We are currently aiming to develop online power optimization techniques for a digital PWM controller. The idea is to minimize the power dissipation of the converter by dynamically adjusting parameters such as the synchronous rectification dead time [5] and the current sharing in multi-phase converters. This work can result in robust, self-optimizing power converters, and can offer new approaches to automatic mode switching (e.g., between continuous and discontinuous conduction mode in PWM converters). The ability of the digital controller to implement complex computation algorithms offers a major advantage for this application.
Figure 1: Block diagram of a digitally controlled PWM converter
  • [1] A. M. Wu, J. Xiao, D. Markovic, and S. R. Sanders, "Digital PWM Control: Application in Voltage Regulation Modules," Proc. IEEE Power Electronics Specialists Conf., Charleston, SC, June 1999.
  • [2] A. V. Peterchev and S. R. Sanders, "Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters," IEEE Transactions on Power Electronics, Vol. 18, No. 1, Pt. 2, January 2003, pp.301-8.
  • [3] A. V. Peterchev, J. Xiao, and S. R. Sanders, "Architecture and IC Implementation of a Digital VRM Controller," IEEE Transactions on Power Electronics, Vol. 18, No. 1, Pt. 2, January 2003, pp.356-64.
  • [4] J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, "A 4 A Quiescent Current Dual-Mode Buck Converter IC for Cellular Phone Applications," accepted for Int. Solid State Circ. Conf., 2004
  • [5] B. Acker, C. R. Sullivan, and S. R. Sanders, "Synchronous Rectification with Adaptive Timing Control," Proc. IEEE Power Electronics Specialists Conf., Atlanta, GA, June 1995

Integrated Power Management for ActiveRFID

Mervin John and Prof. Seth R. Sanders
A representative wireless sensor node contains sensing functions (eg, temperature, pressure, acceleration, strain, chemical, etc.), wireless communication capability, supervisory management, an energy/power source, energy storage, and associated energy/power conversion and management functionality. This research explores the analysis and design issues surrounding integrated CMOS based power conversion and management techniques required in such a wireless sensor device. Fully-integrated switched capacitor DC-DC converters, with no external magnetics, are ideally suited for these types of centimeter and millimeter-scale applications. This research explores techniques for achieving high efficiency over a wide power range (~1uA->~10mA) using minimal die area for the on-chip capacitors.
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